The design of multi-chip power modules is challenging due to circuit asymmetries that can lead to unequal switching losses of parallel-connected devices and hence, uneven temperature distribution. Furthermore, it can potentially cause oscillation of control signals, which, in turn, leads to ringing within the current switching waveforms. Circuit asymmetries come from circuit layout parasitics defined by module design and a parameter spread of SiC power MOSFET dies due to tolerances in the device manufacturing process. Depending on the device design and gate circuit, ringing can violate stability causing a destructive failure of the power devices. Accordingly, dynamic performance of multi-chip SiC power MOSFET modules should not only be characterized by switching losses but also in terms of ringing. This paper aims to evaluate how the parameter spread of SiC power MOSFETs affects the switching stability for a given layout design. The developed simulation framework involves Technology Computer Aided Design (TCAD) process and device modeling, time domain switching circuit simulations of SiC power MOSFETs connected in parallel taking into account a virtual prototype of an in-house-designed Double Pulse Test (DPT) setup with two parallel-connected MOSFETs, and the corresponding frequency domain simulations performed to evaluate quantitatively stability. The proposed modeling procedure will lead to the guidelines for pairing devices based on their electrical performance and circuit layout design, with the aim to ensure reliable and long-lasting operation of multi-chip power modules.