Silicon carbide (SiC) power products may experience voltage degradation which stem from the stacking faults (SFs) growth, commonly known as bipolar degradation (BD). To properly evaluate the BD impact on electric performance of devices it is important to distinguish it from other stress-related degradation e.g., power metal or interconnection. This aspect has not yet been addressed, although the bipolar degradation mechanism is well-understood [1–2]. This work outlines a methodology by modifying the power cycling test (PCsec) to PCmsec to systematically investigate the effect of bipolar degradation while controlling the impact of thermal degradation. This approach enables a thorough evaluation of the distinct influences of both degradation contributors. In this study, we prepared 4H-SiC Merged-PiN-Schottky (MPS) bare dies (650V/10A) with known basal plane dislocations (BPDs) and SFs to evaluate their impact on performance under PCmsec stress. The samples, soldered and Al-bonded on Cu-Si3N4-Cu substrates, were subjected to fast switching in a millisecond to achieve high current density (J) while maintaining low chip junction temperatures (Tvj). The PCmsec stress condition involved a heating time ton = 1 ms and a cooling time toff = 100 ms, as shown in Fig. 1(a). During the PCmsec stress, VF is continuously measured during the heating and cooling phases with high-speed measurement cards in the testbench, applying a 30 mA measurement current (Imeas). Shortly after the heating phase, VF data from 25 – 200 μs was used to extrapolate Tvj, max, using the DUT as a temperature sensor via the Vj (T) method [2]. Before the next heating phase at 100 ms, when the chip reaches ambient temperature (Ta), VF data is used to extrapolate the Tvj, min. As shown in Fig. 1(b), under this condition a high J = 2550 A/cm² was achieved well triggering the device into bipolar operation while thermal degradation is controlled with a Tvj, max = 130 °C well below the chip's solder liquidus point ( 240 °C) and the device Tj max = 175 °C. In contrast, when subjected to 10 ms square pulses almost similar to the condition in [3], the chip's temperature rose to > 520 °C at the same current density, approaching the melting point of aluminum (Al), as shown in Fig. 2(a). This resulted in the chip's destruction and major degradation of the solder interconnects within a few seconds of testing. The transition from the heating phase to the cooling phase introduces switching transients up to the first 25 μs, causing inaccurate Tvj, max measurement. To validate the Tvj, max extrapolation, FEM simulation was performed. The temperature averaged on the chip surface was evaluated as the numerical estimated Tvj, max. At the end of the heating phase, a deviation of 46 °C is shown between the testbench extrapolation and simulation at cycle 9321, as seen in Fig. 2(b). However, using an oscilloscope with a higher sampling rate of 1 μs, the temperature difference aligns closer to the simulated value (~10 °C), ensuring it remains within the acceptable limit. To assess degradation contributions, the diodes went through three post-stress static electrical characterizations: (i) via bond wires, (ii) using a needle probe and not the bond wires and, (iii) again via bond wires to confirm consistency, as shown in Fig. 3. Results indicated deviations between measurements with and without bond wires, underlining the influence of thermal degradation. Photoluminescence (PL) results confirmed bipolar degradation occurring at J > 3.5 times the J nominal value. Overall, a VF shift of below 10% at high current (45A) was observed after subjecting the devices to 100k cycles (~100 seconds) at 2295 A/cm2. In such assembly, the main part of this shift was attributed to bond wire degradation, while the remaining part was linked to top-side Al–power metal reconstruction and recombination-induced stacking faults (SF) causing bipolar degradation. No difference was observed for device rated current of 10 A. Further details will be provided in the full paper.