In order to qualify and characterize the lifetime of semiconductor power packages, the ECPE Guideline AQG 324 [1] defines and describes the corresponding required tests. One of these tests is active power cycle testing (PCT), which necessitates the precise transient measurement of the virtual junction temperature Tvj. For SiC MOSFETs, the voltage drop of the body diode VSD(T) is employed as a temperature-sensitive electrical parameter (TSEP). Recent studies on advanced SiC MOSFETs from various manufacturers demonstrated that the commonly used static temperature calibration method may result in a significant error in the estimation of Tvj [2, 3]. This is due to a novel observed transient behavior of VSD after a gate bias switch with a constant measurement current Imeas and temperature, which leads to a calculation error of Tvj in the range of 10 K. This study continues and deepens the investigation of the effect, examining the influence of those factors that can be adjusted in PCT. The objective is to establish correlations between these parameters and the currently unknown underlying semiconductor physics. Furthermore, methods for minimizing the effect without the additional effort of the proposed advanced dynamic calibration method needs to be identified [2]. The electrical circuit used for this investigation is depicted in Fig. 1. Fig. 2 illustrates the time curve of Tvj, the Drain-Source current IDS, and the Gate-Source voltage VGS are shown for both the conventional PCT load and cooling cycle (right) as well as for the new pattern with no load current to investigate the effect. Using the second scenario, 5 out of 10 devices from different manufactures shows a significant transient shift of VSD after switching VGS from the maximum positive to negative values according to the data sheet. This deviation is designated as ΔVSD, representing the disparity between VSD right after the gate bias switch including device and circuit charging effects, and the end of the cooling cycle toff. This transition of the gate is necessary in power cycling to close the MOSFET channel after the heating phase. Furthermore, the significance and influence of the values of Imeas (10..90 mA), negative VGS (-4..-12 V) and the temperature (20..150 °C) were analyzed in a measurement series. The results, shown in Fig. 4, are divided into blocks for better visualization. The results indicate that a higher negative UGS,off reduces ΔVSD, but is not able to fully eliminate the effect even at -12 V, which is beyond the data sheet limit value for VGS. There is also a clear dependency of the temperature, whereas ΔVSD decreases with higher temperature at low Imeas and increases with high Imeas respectively. A review of the results from 12 individual devices of the same type, as shown in Fig. 5, reveals a high degree of variability among the devices under test (DUT). This underscores the necessity for the recording of individual calibration curves for each DUT prior to the PCT.[1] ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 03.1/2021, ECPE European Center for Power Electronics e.V. ( 2021). [2] J. Breuer, F. Dresel, A. Schletz, J. Klier, J. Leib, M. März, and B. Eckardt, Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling – a Dynamic Approach, in CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems (Düsseldorf 2024) pp. 239–245. [3] M. Noah, C. Fuentes, and F. Filsecker, Dynamic calibration: How to properly estimate junction temperature in SiC MOSFETs subject to body diode voltage shift, in CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems (Düsseldorf 2024) pp. 725–730.