Reliability under blocking has become a hot topic these days for MOS based SiC power devices. Although while running only a single point high temperature reverse bias (HTRB) qualification test at or near maximum rated drain bias and at maximum rated junction temperature can fulfill the qualification requirements for blocking reliability, it does not provide sufficient information to determine device lifetime of SiC-MOS devices during high voltage off-state stress. Like gate bias mediated time-dependent dielectric breakdown (TDDB), to enable blocking lifetime extrapolation at operating condition, the gate oxide (GOX) lifetime modeling using accelerated reverse bias (ARB) stressing which typically employs multiple VDS stress values beyond the rated drain bias but below the avalanche voltage, has become a popular method in the SiC community [1-2]. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where a single stress voltage ARB/HTRB test for a reasonable stress duration can be run to project GOX lifetimes under blocking. Figure 1 shows the median time to fail (MTTF) plot derived from an ARB test where three sets of Wolfspeed 1200 V rated packaged parts were stressed with drain voltage VDS values of 1310V, 1380V and 1450V at 175°C for nearly one year to gather failure statistics. From the failure distribution which follows Weibull statistics, lifetime projection at a reduced operating voltage was then performed by extracting fitting parameters via maximum likelihood estimation and employing a “linear E-model” [3]. Although this method is ideal, it is extremely time-consuming and also challenging for certain devices as depicted above. Figure 2 portrays an alternative approach for off-state lifetime modeling utilizing the “linear E-model” and a single stress voltage failure data obtained from a qualification type HTRB or ARB test running for a certain duration (preferably 1000 hours or more). According to “linear E-model” a blocking lifetime curve can be drawn for any drain bias using TTF = C + gamma * VDS. However, such an estimation will still need the knowledge of either voltage acceleration gamma or intercept C. Estimation of gamma is non-trivial and equally challenging as constructing lifetime curves from multiple drain biases. Conversely, the intercept C represents the lifetime of a device when VDS is extrapolated to 0. At zero gate or drain bias the GOX lifetime is likely determined by the physics of diffusion and subsequent degradation mechanism. Hence the conjecture that Cblocking~CTDDB at VDS,V_GS=0 for a given device technology (identical oxide thickness, drift thickness, cell design etc.) and temperature likely should hold at least for a first order approximation. From the year-long ARB test (Fig. 1) extracted Cblocking~1e13 hours closely match with the CTDDB value obtained from TDDB test done on similar devices at 175°C, further corroborates this assumption. Thus, the knowledge of C value from a TDDB test, along with a known Weibull slope (beta) likely can be utilized to construct a blocking lifetime curve for any failure percentile from a single drain bias stress test data. Figure 3 presents hypothetical scenarios (0 failures after 1000 hours of stressing) of projecting MTTF from a 1200 V rated product for different VDS and C values. In Fig. 3(a), C values are varied from 1e11 to 1e14 hours, while Fig. 3(b) predicts MTTF for various VDS values ranging from 1200 V to 1400 V. Similar projections can be made for other scenarios with various sample sizes and beta values and will be shared in the extended version. Figure 4 discusses some possible shortcomings of this technique. Consideration has been given to scenarios where blocking lifetime estimated from TDDB extracted C value predicts favorable TTF numbers, but lifetime extracted from multiple VDS stress voltages is influenced by an alternative failure mechanism, as shown in Fig. 4(a). In such cases, relying on a single stress voltage may yield an overly optimistic off-state lifetime estimate. However, in such cases the dominant blocking failure mechanism likely will be unrelated to intrinsic GOX breakdown and should be tackled in a manner beyond the scope of this study. Conversely, if the TDDB lifetime is adversely affected by a mechanism other than intrinsic GOX failures, then by virtue of lower C value, the blocking lifetime estimation might get impacted and will project a rather pessimistic value. So, it is imperative to make sure that the C value estimated from TDDB, represents true intrinsic GOX failure mechanism. In conclusion, we present a novel alternative modeling technique to project MOSFET intrinsic GOX lifetime under blocking from a single drain bias stress dataset with the aid of TDDB results done on a similar group of devices at the same temperature which is otherwise extremely time consuming or even impossible to model. The authors would like to acknowledge the valuable discussion with J.W. McPherson in this regard.