SiC CMOS has received increasing attention for integrated circuits operating at high temperatures. To develop SiC CMOS circuits, reduction of threshold voltage (VTH) in SiC p-channel MOSFETs is essential because the VTH is unusually high at the present stage. Although “counter-doping” is a promising technique to reduce VTH, studies on counter-doping (buried channel) in SiC p-channel MOSFETs are very limited. In this study, counter-doped SiC p-channel MOSFETs were fabricated with various Al doses to investigate the effect on VTH reduction. Furthermore, high-temperature operation of SiC CMOS inverters with a logic threshold (VTH,logic) of nearly half of a low supply voltage (5 V) are demonstrated using the counter-doped p-channel MOSFETs.