Name
Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation
Description
A P-iso structure for monolithic integration of planar CMOS and 1.7 kV VDMOSFET on 4H-SiC formed by high energy ion implantation is studied. Design parameters are evaluated by TCAD simulation. The better process condition is then verified by actual test structures. A 2 kV blocking capability is achieved. It is believed that the high energy ion implantation method has the potential to be used in isolation above 3.3 kV.
Speakers
Quan Han Chen - National Yang Ming Chiao Tung University
Date
Friday, October 4, 2024
Time
9:50 AM - 10:10 AM
Location Name
Room 306
Track
Ion Implantation