4H-SiC power devices have proven value in applications like EVs, but future demands require further refinements. While much focus is on moderate power devices, 4H-SiC holds potential for ultra-high-power applications. Key challenges include growing extremely thick, high-quality epitaxial layers with controlled doping and improved minority carrier lifetimes (MCLs) – ideally without post-growth enhancement. For widespread adoption, substrate availability, processing adaptability, and cost must also be addressed. Thick epitaxial layers are crucial for high-voltage power devices, enabling lower doping and reduced conduction losses. Challenges include achieving fast growth rates, maintaining crystal quality over increasing thicknesses, and growth on standard 4°-off substrates. Chloride-based chemistry offers promise for fast growth rates, and together with careful in-situ surface preparation basal plane dislocations (BPDs) replication into epilayer can be minimized. The complexity of controlling defects and surface roughness increases in thicker layers, hence the growth of extremely thick 4H-SiC layers on 4°-off substrates includes distinct challenges compared to prior works on 8°-off substrates [1]. Here we demonstrate the growth of high-quality, 280 µm thick 4H-SiC layers, suitable for 30 kV blocking voltage, on 4°-off 4-inch diameter substrate suitable for advanced ultra-high-power applications. Although our extended presentation will detail how growth parameters impact layer properties, here we mention them briefly together with some of the characterization results for the final 280 μm thick epitaxial layer structure. The epitaxial layers were grown using a chloride-based process with SiHCl3 (TCS) as the silicon source to enable high growth rates. Growth parameters were then optimized to achieve improved quality of epilayers according to the growth rate. Low doping concentrations can be achieved at high growth rates together with increased C/Si ratio following the site competition model [2]. However, above certain growth rates the surface of epitaxial layers gets significantly rough, making the polytype replication challenging. In addition, we have previously shown that the surface roughness is also influenced by choice of different hydrocarbons, both during surface preparation and epitaxial growth [3]. Furthermore, we have found that there is also an upper limit for the C/Si ratio for high growth rates above which the epitaxial layer misses the polytype replicability and turns into polycrystalline SiC. Interestingly, this limit differs significantly for the different hydrocarbons, where even introducing additional chlorine would not change the results. Accordingly, the maximum possible C/Si ratio was then investigated for the different hydrocarbons (here methane and propane) at different growth rates to define the possible window for these parameters. Furthermore, it was also observed that the incorporation of N for a similar N/C ratio will be different for the different hydrocarbons. Next, for the improvement of MCL, growth parameters had to be adjusted in a way that the concentration of the two most important lifetime limiting defects; boron and carbon vacancy related ones, are minimized. Interestingly, the most suitable condition for minimized Z1/2 (low growth temperature and high C/Si ratio) increases the incorporation of boron related defects and vice versa [4]. Thus, the optimum value was found to have the lowest possible of each defect and accordingly improved MCL in as-grown epilayers. Hence, 2.7μs of MCL was achieved for 25μm thick epitaxial layer [4]. Following the fine adjustment of the growth parameters, six full-wafer growth runs with different thicknesses above 125 μm and similar layer structure were grown with slightly varied growth temperature, growth rate and C/Si ratio to investigate the characteristics of each. A summary of the different series of growth runs is presented in Table I. We performed a series of experiments to optimize the growth parameters such as substrate surface preparation, growth temperature and C/Si ratio, under different conditions using CH4 and C3H8 to obtain suitable epilayer properties at different growth rates for thick epilayers. After defining the most suitable growth parameters, epitaxial growth of a low doped 280 μm thick layers was performed. Fig.1a shows the schematic of the layers structure of the thick epitaxial wafer, whereas the cross-section optical image is given in Fig.1b. A highly doped buffer layer was also grown before the growth of 280 µm thick drift layer. Epilayer characterization included DIC optical microscopy, TRPL mapping, Raman spectroscopy, X-ray topography, PL imaging, and CV measurement. Optical microscopy revealed a relatively rough surface with a few triangular defects and short step bunching. TRPL mapping (Fig. 1c) showed an average MCL of ~3μs in as-grown epilayer with no stacking faults except those associated with triangular defects. Comparing the measured lifetime on the thick layer with the one measured on 25μm thick layer, suggests a saturation limit for lifetime in as-grown epitaxial layers grown in our CVD reactor, a more detailed analysis will be presented. Raman spectroscopy verified the epitaxial layer was 4H-polytype throughout the thickness (Fig. 1d). Further analysis of doping and thickness uniformity, X-ray topography and PL imaging will be presented later in detail and different types of defects and their distribution will be discussed. Comparing optical and TRPL maps, with the assumption that nearly all BPDs were converted to TEDs, the calculated yield for (2x2), (4x4) and (10x10) mm2 dies sizes are about 93%, 76% and 50%, respectively.