Name
Fabrication of the planer SiC gate-all-around JFET with channel dose modulation
Description

Currently, SiC is widely recognized as one of the most prominent wide bandgap semiconductors, with expanding applications in harsh environments, such as high temperature and radiation exposure. We developed a planar structure 4H-SiC GAA JFET, where the channel region is formed through ion implantation at varying doses, and its transfer characteristics were evaluated. Moreover, we constructed a common-source amplifier and assessed the maximum voltage gain. We were able to modify the threshold voltage and produce both normally-on and normally-off JFETs by changing the amounts of channel dose. The maximum voltage gain of SiC GAA JFET source-common amplifier is estimated to be −17.1 (24.6 dB), −112.6 (41.0 dB), and −226.7 (47.1 dB) at VDD=10, 20, and 30 V, respectively.

Speakers
Takanori Amamiya - National Institutes of Advanced Industrial Science and Technology - AIST JAPAN
Date
Friday, October 4, 2024
Time
8:30 AM - 8:50 AM
Location Name
Room 306
Track
Ion Implantation