Gate switching instability (GSI) is usually investigated using a gate driving circuit that switches between a negative low level and a positive high level to generate the gate switching stress (GSS). This allows to determine various GSI-dependences like high level voltage, low level voltage, frequency, rise time and fall time [1]. However, these results do not allow clear selection between proposed mechanisms to describe the root cause, because recombination at interface traps, high positive electric field and internal field enhancement all happen within the same time period at the rising edge [2,3]. So, how to modify the experiment to separate these events in time to allow independent investigation? The effect of overshoots and undershoots on GSI by adjusting the gate resistor was investigated in [4]. A further kind of undershoot not connected to a rising or falling edge, may result from the switching transient of the complementary switch in a half bridge, which typically happens while the device is in off-state. How would this undershoot in the off-state effect GSI? A setup to generate three level gate stress pulses was built to address these questions. We use a relay to switch between stress phase and measurement phase. During the stress phase source and drain are shorted and driven by a gate driver IC with 20% duty cycle at 500 kHz. The gate is driven at the same frequency and duty cycle by a second independent channel of the IC. Voltages and delay between the driver channels are set such that we obtain the stress voltage sequence shown in Fig 1. Note that the intermediate voltage at +4 V is such that the interface is expected to be in inversion. The legend indicates the delay between rise time of the negative pulse and rise time of the positive pulse of each curve shown. We used commercially available devices (IMBG120R234M2H) with a small gate capacitance to allow fast switching without oscillations despite the relay in the drive path. Both stress and measurements were done at room temperature. To separate the threshold voltage drift (Vth-drift) due to GSI from the Vth-drift originating from the constant voltage stress (BTI), we included an aggressive preconditioning before each Vth-measurement by applying the low level for 1 s and applying the high level for 1 s and repeated that 5 times. The Vth was measured with gate and drain shorted and forcing -0.9 mA at the source contact. The Vth measured with positive pulse sequence from Fig 1b does not show any drift, as shown in Fig 2a, indicating that the preconditioning is sufficient to avoid Vth-drift from BTI. The curve from the negative pulse sequence shows a significant drift, indicating that even with low positive voltages, GSI is triggered effectively. The three level stress pulse sequences all show very similar Vth-drift curves. A close-up of these curves in Fig 2b shows that the Vth-drift slightly increases with reduction of the delay between negative and positive pulse in the three-level stress sequence. The internal field enhancement happens when going into inversion and, according to [2], is expected to cause an enhanced Vth-drift corresponding to an increase of 10 V~20 V for <100 ns in the gate source voltage for BTI. Because the Vth-drift depends only slightly on the delay before a +16 V boost of the gate-source voltage, we conclude that a major part of the Vth-drift cannot be explained by the internal field enhancement. Fig 3a shows the oscilloscope traces of the applied stress voltage sequences to investigate the effect of an additional negative pulse during the off-state. The trace without negative pulse is used as a reference. Fig 3b shows that the negative pulse significantly increases the Vth-drift and that the delay between the pulses, does not make a significant difference. Further investigations are needed, but it seems that in circuit design focused on optimizing for low GSI, we need to take care to reduce the negative amplitude of transients in the off-state.