Several 1.2kV 4H-SiC devices of various cell architectures have been successfully fabricated by employing different P+ implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities for each of the different device designs. It was found that by utilizing devices designed with an orthogonal P+ source layout as opposed to the traditional P+ stripe pattern or by utilizing the unipolar current of the JBSFET, the long-term reliability under continued 3rd Quadrant current stress can be greatly improved even in devices with medium to high BPD densities.