A new topological layout was explored to increase the channel density of 1.2kV 4H-SiC MOSFETs. The novel 'Ladder' MOSFET features an additional JFET and channel region inserted orthogonally in the layout (see Fig. 1). Unlike previous approaches to increase channel density [1], the proposed Ladder design maintains a stripe pattern. To fairly compare, the same design rules were applied for both MOSFETs. However, the half contact width (WC) slightly differs due to limitations within these rules, with it being 0.7 µm and 0.9 µm for the Nominal and Ladder MOSFETs. Consequently, the cell pitches for the Nominal and Ladder MOSFETs are 5.4 µm and 5.8 µm. The channel density, calculated by dividing the channel region area by the total unit cell area, was calculated to be 0.30 and 0.41 for the Nominal and Ladder MOSFETs, respectively. 3D Synopsys Sentaurus TCAD simulations were employed to conduct a comparative analysis between the Nominal and Ladder MOSFETs. Utilizing SProcess, 3D doping profiles were generated under identical implantation and process conditions, as depicted in Fig. 2 for both the Nominal (a) and Ladder (b) MOSFETs. Subsequently, forward and transfer characteristics were simulated using SDevice. The specific on-resistance (Ron,sp) was determined to be 3.96 mohm⋅cm2 and 3.60 mohm⋅cm2 at Gate Voltage (VG) = 20V and Drain Voltage (VD) for the Nominal and Ladder MOSFETs, a 10% reduction in Ron,sp. Threshold voltage (Vth) was found to be 2.53 V and 2.33 V for the Nominal and Ladder MOSFETs, respectively, when assessed at VD = 0.1 V and ID = 1 mA. As shown in Fig. 3 and 4, the newly developed 3D simulation methodology was effective in predicting trends in the static electrical characteristics for different MOSFET topological layouts. Detailed descriptions of the 3D simulations will be discussed in the full paper. To further compare, both Nominal and Ladder MOSFETs were fabricated on 1.2kV rated epi-layer with 360 µm 4H-SiC substrates at Clas-SiC Wafer Fab in the United Kingdom, employing an identical process flow and implantation recipes. A self-align process was implemented to form the Pwell/Channel. Subsequently, the wafers were diced, and from each, 15 Nominal and 10 Ladder MOSFETs were selected for packaging in TO-247s. Comprehensive measurements of static electrical characteristics were conducted. At a VG = 20V and Drain Current (ID) = 15 A the Ron,sp for the best performing Nominal and Ladder MOSFETs was determined to be 3.84 mohmcm2 and 3.40 mohmcm2, showcasing a notable 12.94% reduction in Ron,sp for the Ladder MOSFET. The typical output characteristics of these selected MOSFETs are illustrated in Fig. 5. Overall, Ladder MOSFETs exhibited an average reduction of 15.39% in Ron,sp compared to their Nominal counterparts, as evidenced in Fig. 6. Additionally, the average threshold voltage (Vth) at ID = 5mA and when VG=VD was measured to be 2.49 V and 2.29 V for the Nominal and Ladder MOSFETs, respectively. The enhancement in Ron,sp achieved through the utilization of the Ladder MOSFET design is consistently sustained even at elevated temperatures, as depicted in Fig. 7. It is interesting to observe that the temperature coefficient of the Ladder MOSFET is smaller than that of Nominal MOSFET, which may be attributed to wider contact opening.