SiC MOSFETs designed with various hexagonal unit cell layouts are shown in Fig. 1(a-c). These unit cell layout designs are identical in all aspects except for the existence/non-existence or the shape of Shield and Bridge regions, formed by the PWELL implantation. A Shield region links adjacent PWell hexagons. Design A in Fig. 1(a) has no Shield region. Design B in Fig. 1(b) has two variants (B1 and B2) of a triangular Shield region. Design C in Fig. 1(c) has two variants (C1 and C2) of a tetrapod-shaped Shield region. In addition, Design C has Bridge regions of different widths that connect the Shield region with the adjacent PWell hexagons. Table I summarizes the various unit cell designs with the Bridge widths (normalized to Design B1) and the channel densities (normalized to Design D). Design D in Fig. 1(d) has a conventional stripe layout. Fig. 2 shows top-down SEM images of the unit cells of the fabricated SiC MOSFETs with Design B2 and Design C2. The intricate interaction of the processing steps for PWell and N+ Source region formation with the as-drawn sub-micron bridge and shield features result in additional features not present in the mask layouts. For instance, the N+ source regions may also be formed within the shield/bridge regions, as observed from the SEM images in Fig. 2. Further, these N+ source regions may or may not be connected to the N+ source region within the main PWELL hexagons, which results in changes to the effective channel width. All the SiC MOSFETs investigated in this work were rated at 650 V and had a chip size of 3.06 mm2. Apart from the layout variations described above, all the MOSFETs were fabricated using Navitas’s GeneSiCTM “trench-assisted planar” SiC MOSFET architecture, which is distinguished by the PPLUS regions formed below a trench etched into the SiC in the Source regions. All Designs, except Design D from Wafer A, show VTH of ~ 3 V (Fig. 3). Design B1/B2 and Design C1/C2 with the shield/bridge regions show a median RDS,ON around 102~106 mΩ (Fig. 3). Direct comparison of Design C1/C2 to Design D from Wafer B shows 13.6% reduction of RDS,ON, which is due to the hexagon PWell geometry with > 2X channel densities. Design A with no shield shows the lowest RDS,ON of 92.7 mΩ. Design C1/C2 show 2-3% lower RDS,ON than Design B1/B2, due to the unique tetrapod-shaped shield region of Design C1/C2 reduces the JFET effect, in addition to a 10% higher channel density (calculated from the mask layout). Design D from Wafer A has a 10% higher VTH as a result of a longer effective channel length, when compared to the hexagonal layouts. The drain leakage plot at the bottom of Fig. 3 shows the spatial distributions of the IDSS measured at 650 V, where 0 and 60 on the horizontal axis indicate the center and edge of the wafers, respectively. Design D shows the best IDSS performance, while Design B1/B2/C1/C2 having the shield/bridge regions show significantly lower IDSS compared to Design A, which is unshielded. Fig. 4 shows a plot of the RDS,ON vs. TC. Temp-co was calculated by using the RDS,ON‘s at RT and 150ºC. Design A with no shield region shows the lowest temp-co. of 1.08, which is far better (by ~17%) than Design D from Wafer B with the same VTH of 3V, and this is due to the reduction of the JFET resistance in Design A compared to Design D because of the lack of the shield/bridge regions. Design B2 and C2 have temp-co’s of 1.21 and 1.20, respectively, which are ~10% higher than Design D from Wafer B. Fig. 5 shows the HTGB results (up to 500 hr) on select designs (Design B2/C2/D). Design B2/C2, which are better designs than Design A due to existing shield/bridge regions, have less VTH shift than Design D with better statistical tightness. This suggests the shield/bridge regions of Design B2/C2 provide better protection to their gate oxide stacks in comparison to Design D. It should also be noted that there is a four-sided JFET depletion effect in the shielded/bridged devices (Design B2/C2) as compared to the stripe layout (of Design D) which only has a double-sided JFET depletion effect. This leads to a smaller EOX (at the center of the JFET region) under high drain bias. Design B2 is slightly better than Design C2 from HTGB perspective due mainly to the larger area of its shield region.