Silicon Carbide (SiC) based devices have become mainstream for power applications rated from 1-3.3kV [1]. However, grid scale, defense and pulsed-power applications require higher voltage rated devices such as insulated gate bipolar transistors (IGBTs) with very high reliability operation and high surge current capability. Basal plane dislocations (BPDs) can cause stacking fault (SF) expansion during IGBT operation, which results in forward voltage degradation, and higher reverse leakage currents. Developments in epitaxial growth over past two decades have successfully achieved almost BPD-free epitaxial layers by converting BPDs to threading edge dislocations. However, under surge current conditions, very high carrier injection can occur and cause BPDs to propagate from substrates into the epitaxial layers causing device failure [2]. In this work, we investigate BPD faulting under very high carrier injection in engineered SiC substrates SmartSiC™ and compare it to monocrystalline substrates, and also analyze any associated stacking fault expansion in epitaxial layers deposited on both the substrates. For this work, 10 µm thick, 1x1016 cm¯³ n-doped epitaxial layers with 2 µm thick, 1x1018 cm¯³ n-doped buffer layers were simultaneously grown on a 150 mm diameter engineered substrate and a commercial monocrystalline SiC substrate. The SmartSiC™ substrate consists of less than 1 µm thick monocrystalline SiC layer transferred on to a thick polycrystalline SiC substrate using the Soitec SmartCut™ layer transfer process process. Full wafer ultraviolet photoluminescence (UVPL) imaging was performed using a 4W, 355 nm UV laser coupled to a custom microscope setup. Above bandgap UV excitation creates electron-hole pairs in SiC, which simulates current injection during device operation. Ultra-high carrier injection was performed in several 2.5x2.5mm² areas in both wafers by UV excitation with 100–10,000 Wcm¯² power densities. The stress duration varied from 5-30 mins for different stress conditions. UVPL imaging was followed after each stress condition to evaluate BPDs in the epitaxial layers. Upon UV illumination at 100 Wcm¯² for several minutes, no BPDs were observed for all regions analyzed. Successive UV stressing at 1500 Wcm¯² caused BPD faulting in the monocrystalline substrate and propagation into the epitaxial layer, which was directly observed from the UVPL images. Upon stressing few regions in the engineered substrates at 1500 Wcm¯², no BPD faulting or expansion was observed in any of the regions. Following this, some regions in the engineered substrates were stressed at over 10,000 Wcm¯², which also did not cause any BPDs to expand into the epitaxial layer. To understand potential reasons that apparently makes the engineered substrates less prone to BPD faulting, estimates of carrier densities were simulated for the UV stress conditions. Typical carrier lifetimes were assumed as: 1µs for drift layer, 200ns for buffer layer, 100ns for monocrystalline substrate and 50ns for thin transferred substrate. During carrier injection, the engineered substrate has fewer carriers due to limited thickness of the transferred layer and lower carrier lifetime, which mitigates the possibility of recombination at BPD partials causing any expansion. The thin transferred layer also has fewer BPDs. For the monocrystalline substrate, the carrier density is sustained for several micrometers at ~5x1017 cm¯³, which is sufficient to cause BPDs to fault and expand into the epilayer. An additional component for BPD glide is wafer strain. The engineered substrate could potentially have lower strain due to high flatness. Precise lattice strain and tilt maps from x-ray rocking curve mapping [3] comparing both the wafers will be also be presented.[1] Z. Chen and A. Q. Huang, Mater. Sci. Semicon. Process. 172, 108052 (2024) [2] N. A. Mahadik, et. Al., Appl. Phys. Lett., 100, 042102 (2012) [3] N. A. Mahadik, et. Al., Sci. Rep. 10, 10845 (2020)