We developed a new self-aligned process to suppress short-channel effects (SCEs) in SiC UMOSFETs with a short channel length (Lch). By this process, n+ source, p+ contact, p+-shielding region at the bottom of the trench, and SCEs suppression structure (SCEs-SS) were formed symmetrically to the trench without increasing the concentration at the channel surface. SiC UMOSFETs with Lch = 0.28 μm has been successfully realized without SCEs such as drain-induced barrier lowering and punch-through. As a result, specific on-resistance (RonA) was reduced by 14 % from Lch = 0.46 μm, and the trade-off between short-circuit withstand time (tSC) and RonA was improved owing to the low channel resistance / JFET resistance ratio. The developed self-aligned process is expected to contribute to the realization of SiC UMOSFETs with extremely low RonA and high tSC.