Silicon carbide (SiC) epi-wafers, with thick epitaxial layers required for high-voltage applications, are prone to warping and having basal plane dislocations (BPDs) form due to the lattice mismatch between the epilayer and substrate during the manufacturing process. These problems must be solved to improve yields, particularly for large-diameter wafers. Our previous study revealed that BPDs are generated mainly from triangular defects in SiC epi-wafers at epilayer thicknesses of 50 μm or more. In this study, we classified the observed BPD half-loops into two types and aimed to elucidate how the BPDs formed, from the perspective of the behavior in the wafer and numerical stress analysis. Fig. 1 shows synchrotron x-ray topography images and their schematics of the 4° off 150 mm-diameter epi-wafer with a 200-μm thick n− epilayer (Nd−Na=~2×1014 cm−3) after polishing the n+ substrate (Nd−Na=~5×1018 cm−3) leaving ~3 μm. As the transmission image (g=11¯20) in Fig. 1(a) shows, BPD half-loops were generated by triangular defects in the epilayer and extended wide on the basal plane. Noteworthy, however, is the relatively small density of BPD having propagated from the substrate into the epilayer (<0.07 cm−2). Many of the BPD half-loops from the triangular defects reach the crystal surface on the substrate side, indicating that the BPDs propagated beyond the epilayer/substrate (epi/sub) interface into the substrate. Also worth noting is the fact that the BPD half-loop is narrower at the epilayer surface and widens as it approaches the epi/sub interface. Fig. 1(b) shows a reflection topography image with a penetration depth of ~12 μm taken from the C-face (g=11¯2¯8). As shown in the figure inset, the BPDs propagating perpendicularly or obliquely to the step flow direction exhibit dark contrasts, which correspond to edge-type BPDs with an extra half-plane above the BPD core (epilayer side) [1]. Some of the BPD half-loops have segments with edge components near the epilayer surface and the inside of the substrate, with an extra half-plane below and above the BPD core, respectively, as the schematic of Fig. 1(c) shows. These BPD half-loops propagating into the substrate are hereinafter referred to as Type-A. Conversely, BPD half-loops of the opposite sign were also observed, as shown in Fig. 2. The transmission topography image (g=11¯20) shows that BPDs of this type form interfacial dislocations (IDs) at the epi/sub interface and are narrower than that of Type-A BPDs. Confirming the dislocation contrast in the reflection topography image taken from the C-face (Fig. 2(b), g=11¯2¯8), the IDs appear as bright contrasts, corresponding to edge-type BPD with an extra half-plane below the BPD core (substrate side). Such BPD half-loops forming IDs are referred to as Type-B. For these two types of BPD half-loops, their widths in the [1¯100] direction at the epi/sub interface in epi-wafers with epilayer thicknesses of 50, 100 and 200 μm are examined based on the topography image and plotted as shown in Fig. 3. BPD formation from triangular defects was observed only for an epilayer thickness of 50 μm or more. As for the Type-A, it is evident that the BPD width increases with epilayer thickness, about 10 mm wide for a 200-μm epi-wafer. Conversely, for Type B, although the width appears to increase gradually with epilayer thickness, the tendency is far less compared to Type A. The stress caused by the differing coefficient of thermal expansion between the n− epilayer and the n+ substrate is considered one of the driving forces for generating and increasing the width of the BPD half-loops. Fig. 4 shows the calculation results of the stress σrr acting on the BPD located 5 μm below and above the epi/sub interface (substrate side), using a two-dimensional axisymmetric model based on the finite element method, assuming coefficients of thermal expansion for the epilayer and substrate of 5.70×10−6 and 5.22×10−6 K−1, respectively [2]. Here, a uniform temperature distribution is assumed. The lattice constant of the epilayer is assumed to be larger than that of the substrate, resulting in compressive (σrr < 0) and tensile (σrr > 0) stresses on the epilayer and substrate. As the epilayer thickens, the tensile stress on the substrate increases while the compressive stress (<0) declines. These stresses can qualitatively explain the driving forces of the two types of BPD half-loops that form. The observed widening of Type-A BPD in the substrate across the epi/sub interface can be attributed to the tensile stress acting on the substrate. The tendency for the Type-A BPD half-loops to widen with increasing epilayer thickness is also consistent with the stress calculation. Conversely, Type-B BPD tends to mitigate the compressive stress in the epilayer and any slight change in width observed with respect to epilayer thickness can be attributed to reduced compressive stress with respect to the epilayer thickness. Since other possible driving forces, such as thermal stress caused by the radial temperature distribution and local stress near the nucleation point (triangular defects), can affect the formation and width of BPD half-loops, these effects also need to be considered, e.g. to discuss the in-plane distribution of BPD half-loops.