Name
Achieving Low Dit (~5×1010eV-1cm-2), Competitive JG (~ 5×10-10 A cm-2) Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide
Description
In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the SiO2/SiC MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density (~ 5×1010 eV-1cm-2), robust flat-band voltage stability under positive bias stress, and decent leakage current density (JG ~ 5×10-10 A cm-2) can be unambiguously verified after nitric oxide (NO) gas post-deposition annealing.
Speakers
Umesh Chand - IME A*STAR, Singapore
Date
Wednesday, October 2, 2024
Time
12:10 PM - 12:30 PM
Location Name
Room 306
Track
Stress & Threshold Voltage Instabilities