The current SiC high-power device technology utilizes the Si-face SiC substrate, benefiting from high-quality interface and a large band-offset between the Si-face SiC and the gate oxide layer. However, carbon-face (C-face) SiC devices show potential due to their unique properties. First, a superior epitaxy process offers a large growth window and lower defect density [1]. Second, there is less defect generation during post-implant activation due to its higher polytype stability as compared with Si-face [2]. For trench device formation, the faster oxidation rate of C-face SiC compared to other crystal planes provides up to 3× thicker oxide at the trench bottom compared to the sidewalls, enabling simpler fabrication with improved gate breakdown voltage for C-face trench devices, despite the low band-offset between SiO2 and C-face SiC [3]. Moreover, C-face SiC enables graphene growth and new device architectures. There are few reports of epitaxy on C-face SiC, with most focused-on lab-scale processes using small size wafers [4]-[6]. Miyasaka et al. [5] reported epitaxy on 150 mm C-face SiC, but the growth rate is ~10 – 11 µm/h and defect density was ~ 0.9 cm-2. This paper reports the highest speed epi growth (~ 50 µm/h) on 150 mm C-face SiC and achieves a record-low defect density of < 0.1 cm-2.