Anisotropy of SiC crystals leads to significant variance of their physical properties in different crystallographic directions and planes. In particular, it is well known that SiC channel mobility strongly depends on the chosen crystallographic direction [1], and a trench gate has a higher channel mobility than a planar one [2]. Other advantages of MOSFET trench geometry over a planar design include lower on-resistance, reduced conduction and switching losses and elimination of the JFET region [2, 3]. Nevertheless, these benefits come hand in hand with lower short-circuit tolerance and challenges of optimizing such MOSFETs for reliable and robust operation [3, 4]. Moreover, to our knowledge, apart from mobility [1] and mechanical characteristics studies [5], other differences between various crystallographic orientations perpendicular to c plane have not been thoroughly investigated yet. In this paper, we study the influence of trench orientation on threshold voltage shift (ΔVth) and its recovery in ultra-fast bias temperature instability (ufBTI) experiments and density of traps using the charge pumping (CP) technique. The prototype vertical trench devices used in this study were fabricated with several different trench orientations: 0° (anti-m) and 180° (m), 90° (anti-a) and 270° (a), along with intermediate 45°, 135°, 225° and 315° orientations. It is worth noting that due to standard 4° miscut of SiC wafers, only 0° and 180° coincide with true anti-m and m crystal planes, while all other listed trench configurations are 4° off from the corresponding crystal plane in one direction or the other. All measurements were performed on wafer level, each device had four contacts: drain at the backside of the wafer, source, gate and a separate p-body contact at the wafer surface. The gate oxide is a deposited SiO2 layer with subsequent NO anneal. The oxide thickness was 50 nm. We used the following equipment: Cascade microchamber attoguard Summit 11201B manual probe station and parameter analyzer Keithley S4200-SCS equipped with a 4245-PMU card, two 4225-RPMs and a 4200-PA preamplifier. In ufBTI, for each combination of stress conditions (gate voltage Vg=18/−5 V, stress time 10 μs/10 ms/10 s), six devices per trench orientation were stressed, and then ΔVth recovery data was collected. Box plots of recovery data obtained after 10 ms of stress at two different gate voltages are shown in Fig.1 (left panel) along with extracted median values of |ΔVth| for four recovery times (right panel). It can be clearly seen that (1) for positive BTI, three trench orientations have the smallest ΔVth values: 225°, 270° and 315°, with 270° (a) standing out; (2) for negative BTI, two trench orientations have the largest ΔVth values: 0° (anti-m) and 180° (m), while 45°, 135°, 225° and 315° orientations show comparable ΔVth values which are slightly better than the ones of 90° (anti-a) and 270° (a). These results are in line with the ones obtained at 10 μs and 10 s of stress. In CP, the data was collected at f=1MHz, trise=tfall=100 ns, duty cycle 50%, pulse amplitude 6 V. Three devices of each type were measured to get one CP curve shown in Fig. 2 (left panel). Peak ICP (and, consequently, the density of interface traps) decreases in the following order: 0° (anti-m) and 180° (m), 45° and 135°, 315°, 90° (anti-a) and 225°, 270° (a). One can also notice a ‘shoulder’ peak on the rising edge of CP curves for 90° (anti-a), 225°, 270° (a) and 315° orientations corresponding to donor states close to the valence band. Clearly, the density of these states should be the highest for 270° (a) configuration. Finally, we extracted threshold voltage and resistance for different trench orientations from their IDVG characteristics (Fig. 2, right panel). Although 225°, 270° (a) and 315° trench configurations demonstrate significantly lower resistance than the others, it comes hand in hand with a lower threshold voltage. [1] H. Yano, H. Nakao, T. Hatayama et al., Materials Science Forum 556-557, 807 (2007); [2] R. Siemieniec, D. Peters, R. Esteve, W. Bergner, D. Kück et al., in Proceedings of the 19th European Conference on Power Electronics and Applications (2017); [3] C. Langpoklakpam, A.-C. Liu, K.-H. Chu, L.-H. Hsu, W.-C. Lee et al., Crystals 12, 245 (2022); [4] J. Wang and X. Jiang, IET Power Electronics 13 (3), 445 (2020); [5] S. Shi, Y. Yu, N. Wang, Y. Zhang, W. Shi et al., Materials 15, 2496 (2022).