In medium-voltage applications (> 3.3kV), the predominant devices are SiC MOSFETs (Fig. 1(a)) and Si IGBTs. However, these devices face challenges such as high conduction losses for SiC MOSFETs and significant switching losses for Si IGBTs. Consequently, vertical high-voltage 4H-SiC superjunction (SJ) (Fig. 1 (b)) devices present a superior solution, offering improved conduction and switching characteristics. SJ devices exhibit a better trade-off between the specific on-resistance RON,sp and the breakdown voltage (BV) (RON,sp ∝ BV) to the conventional, uniform doped, vertical power devices (RON,sp ∝ BV2.3) as shown in Fig. 2 [1]. The imperative design of SJ devices is the alternating P and N pillars, where the thickness determines the breakdown voltage and their widths and doping influence the specific on-resistance. Fabrication of SJ devices necessitate precise processes involving multiple steps to ensure the desired charge-balanced pillars, particularly for thicker high-voltage pillars. Various techniques have been explored, including multi-epitaxial growth [2], trench-refill processes [3], and a series of MeV implantations and epi-growth processes [4]. However, these methods contribute significantly to the overall cost of SJ devices, potentially outweighing their benefits compared to conventional devices with similar breakdown voltage and current ratings. This paper conducts a comparative analysis of chip costs between SJ and conventional MOSFETs at specified breakdown voltage and current ratings, shedding light on the economic feasibility of SJ devices in 4H-SiC. We construct our cost model referring to GE’s previous study [4], leveraging their scalable devices that exhibit no performance degradation compared to other fabrication methods [2, 3]. We used the closed form set to calculate the performance parameters as a function of drift layer thickness for conventional MOSFETs [5]. For SJ MOSFETs, we employed the empirical formula developed by [6] for the blocking performance (BV) and [7] for the conduction performance (RON,sp). Additionally, we validate our static calculations through TCAD simulations. To estimate the active area for both devices, we have used Eq. (1), which is a thermal-based analysis developed in [8]. Assuming a JTE and periphery width for both devices to be 10µm + 5×drift layer thickness; the chip size can be estimated to calculate the total chip cost from using Eq. (2). For conventional MOSFETs, the substrate and fabrication costs are assumed to be $2000 plus a $50/µm for epitaxial growth cost, while SJ MOSFETs incur an additional cost of $3000 (or a variable as seen in Table 1) to produce 12µm pillar structure [4]. Table 1 outlines our assumptions for SJ MOSFET costs with different chip designs; the breakdown voltage crossover (see Fig. 3), where the chip price for both conventional and SJ MOSFETs become even is ~ 14kV for the baseline Chip#1 design. A $1000 reduction in pillar manufacturing cost can reduce the crossover to 8.5kV, yielding a 41% advantage for SJ MOSFET (Chip#2). When increasing the yield to 0.8 (to match that of conventional) or decreasing pillar width to 1μm (technological limit) can enhance it to 46 and 47% (Chip#3 and #4, respectively). Chip #5 reflects the lowest BV crossover achievable (Fig. 4). This analysis underscores the potential improvements in the SJ fabrication process and design to enhance its cost-effectiveness to benefit from its low RON,sp especially at higher BV ratings. The design methodology, cost model, and underlying assumptions will be elaborated upon in greater detail in the full paper.