Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are progressively displacing Si in lower voltage classes. However, in high voltage applications (>3000V), their conduction losses match those of Si IGBTs. To address this, Superjunction (SJ) and semi-superjunction (SSJ) technologies have been proposed to enhance the tradeoff between conduction losses and breakdown voltage (BV). Nonetheless, commercializing these designs encounters hurdles due to the intricate formation of deep P-type pillars. Recently, cost-effective methods for fabricating Schottky Barrier Diodes (SBDs) were introduced, advocating for a semi-superjunction design employing oxide-filled trenches and P-doped sidewalls to facilitate the superjunction effect with minimal implantation depth. This study proposes a 3.3 kV SSJ SiC MOSFET utilizing such techniques, potentially reducing fabrication costs. TCAD simulations assess the performance of standard planar structures, planar MOSFET Semi SJ (P SSJ), and trench MOSFET Semi SJ (T SSJ) devices. Static characteristics, including charge balance analysis, are examined, alongside a proposed solution involving a graded doping top epitaxial layer to maintain an equal charge balance. The expected result is an additional 4.9% reduction in specific on-state resistance (RONSP), compared to a uniform doped top layer. In conclusion, the proposed semi-SJ structures aim to decrease RONSP by 35.5% and 46.8% for planar and trench configurations, respectively, while ensuring ample sidewall implantation space and comparable off-state performance.