Silicon Carbide (SiC) power devices are of great interest for high power density, high switching frequency, and high voltage applications, including radiation environments such as space missions and particle accelerators. They offer better thermal conductivity and breakdown field than Si and GaN devices, allowing for device designs with larger current ratings, lower on-state resistance, and higher breakdown voltage for a given die size compared to their silicon device counterparts. However, like their silicon counterparts, SiC power devices are also susceptible to single-event effects (SEEs) defined as a perturbation of the normal operation of the component induced by a single ionizing particle. For power MOSFETs, single ions can cause catastrophic failures such as single-event burnout (SEB) and single-event gate rupture (SEGR), or permanent degradation leading to gradual increases in drain and gate currents, known as single-event leakage current (SELC) [1]. SELC usually occurs at lower biases than SEB or SEGR when irradiated under identical conditions. However, even below the SELC threshold, at low drain biases, SiC MOSFETs may exhibit latent damage to the gate oxide, as previously studied in [1−4]. In this case no electrical degradation is observed during the exposure, but the oxide rupture can be induced when applying additional electrical stress after the irradiation. Gate oxide degradation is more critical in SiC MOSFETs than in Si MOSFETs because of the smaller gate oxide thickness and the higher electric field that develops across the gate oxide in SiC MOSFETs. The effect of different parameters on the sensitivity to latent damage such as the gate layout, the total amount of ions, their energy and the VDS is still under debate and will be further explored in this work, being a critical problem for the long-term device reliability for radiation hardness. In this experiment, heavy-ion irradiation was performed with two variants of high voltage MOSFETs, as shown in Fig. 1 at the University of Jyväskylä Radiation Effects Facility (RADEF) with 2059 MeV xenon ions, with a linear energy transfer (LET) of 49.1 MeV/(mg/cm2) (i.e., the energy deposited per unit distance). The low epi-doping MOSFET variant has a breakdown voltage (BVDSS) of 4500 V, whereas the high epi-doping MOSFET variant has a BVDSS of 1800-2300 V. The structural difference between the devices is their different doping of the N- drift layer (the epitaxial layer). These devices were irradiated up to a drain-source bias of 200 V at different total fluences during each run, and both devices suffer latent gate oxide degradation when irradiated with Xe ions. Post-irradiation, the devices were stressed under a gate-source (VGS) bias from -5 V up to 20 V, and the IG-VGS responses were recorded. Table 1 shows the device responses when a constant voltage bias was applied, and the heavy-ion fluence was increased by one order of magnitude in every subsequent irradiation run on the same device. The results suggest that the different epitaxial layer doping and the pre-strike electric fields across the gate oxide and within the device between the two variants plays a negligible role in their latent damage responses. As shown in Figs. 2 and 3, both devices suffer gate oxide breakdown (i.e., reaching current compliance) under similar test conditions. The experimental data suggest that latent gate damage is unlikely to occur when very few ions strike the JFET region of the device, which is an important aspect to understand for space applications (102 fluence in Table 1). At total fluences of 103 and 104 ions/cm2, which is low compared to previous studies [1-4], the probability of a single ion striking the JFET region is high. A likely cause for a single ion causing the latent gate damage could be the electric potential dropping and collapsing across the gate oxide, as shown by the 2-D TCAD simulations, and their corresponding 1-D cutlines shown in Figs. 4 and 5. However, at these low ion fluences, the probability of multiple ions striking in the same local area of the JFET region is low, hence it is unlikely that latent gate damage is due to a cumulative effect.