This work assesses the field effect (FE) mobility and threshold voltage variation of both SiC n- and p-MOSFETs from room temperature (RT) to 400 ̊C and determines their stability under various stress conditions. Following this assessment, the high-temperature performance of thermally grown oxides and deposited oxides are compared, highlighting the superiority of the deposited gate oxide stack. Bias temperature instability (BTI) from RT up to 400 ̊C was conducted under ±25V of DC stress. For n-MOSFETs, the VTH shift was less than 3% even after 400 ̊C of DC stress. However, for p-MOSFETs, there are significant changes in VTH at HT. The results also indicates that the thermal oxides can operate up to 200 ̊C while UT+Thick CVD can operate up to 300 ̊C without significant degradation. Removal of stress and temperature result in complete recovery of n-MOSFETs however p-MOSFETs suffer a permanent shift in VTH. This indicates generation/activation of deep oxide traps near EV. Fig. 3 shows that there is no degradation of mobility for n-MOSFETs while the p-MOSFETs suffer mobility reduction above 300 ̊C after BTI stress. In conclusion, SiC CMOS devices maintain strong performance up to 400 ̊C. However, while n- MOSFETs recover well post-stress, p-MOSFETs show significant threshold voltage shifts and mobility reductions at high temperatures, underscoring the need for improved passivation near valence band. In addition, deposited oxide stacks demonstrate superior reliability compared to thermal oxides.