NASA Glenn Research Center has previously reported the world’s first and only semiconductor integrated circuits (ICs) to demonstrate stable electrical operation for over a year at 500 °C [1]. However, these initial prototype 4H-SiC Junction Field Effect Transistor-Resistor (JFET-R) chips were of limited circuit complexity (< 200 transistors per chip) and require detrimentally higher voltage, current, and power compared to functionally equivalent conventional-temperature silicon chips. Further upscaling of circuit complexity while reducing power consumption is clearly crucial towards realizing impactful infusion of SiC JFET-R ICs into extreme environment applications. This ICSCRM 2024 submission compares design layouts and circuit simulations of the next two planned SiC JFET-R IC prototype fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. These designs are based upon foundational mask layout and first-order SPICE model approximations calculated and posted online for these respective technologies [2]. Even though both generations employ the same physical JFET gate length (3 µm) and chip size (5 mm x 5 mm), SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are: (1) IC Gen. 13 n-channel epilayers are both thinner (Fig. 1) and completely uniform across each wafer, and (2) the switch to stepper-based photolithography for IC Gen. 13 enables smaller layouts to be implemented for functionally identical circuit blocks (Fig. 2). Fig. 3 exemplifies the calculated disparity in 500 °C JFET drain current characteristics that arise primarily from the difference in n-channel layer thickness. As seen in Table I, the resulting lower JFET threshold voltage (VT0) in enables power-saving ≥ 2-fold reductions in IC power supply and logic signal voltages for fundamental IC Gen. 13 logic circuits. Table II quantitatively compares application-relevant circuit metrics obtained for the most complex circuits that were designed and SPICE-simulated for prototype implementation in both IC Gen. 12 and IC Gen. 13. As seen in the right column, substantial ≥ 2X improvements in both chip functionality (e.g., memory capacity) and chip power are simultaneously realized for IC Gen. 13 designs over IC Gen. 12. In contrast to muti-chip circuit boards required to realize microprocessor and Venus lander control circuit functionalities in IC Gen. 12 technology, IC Gen. 13 enables highly advantageous monolithic single-chip circuit realization. Such “system on a chip” implementation impactfully improves system power consumption, packaging reliability, and physical compactness. So long as other factors (such as IC robustness) are not compromised, the superior capabilities of IC Gen. 13 can be expected to pave the technical path for further maturation, manufacturing, and beneficial application infusions of 500 °C durable SiC JFET ICs. Acknowledgements: This work was conducted by The NASA Glenn Research Center in Cleveland, OH USA with funding from the NASA Science Mission Directorate under the High Operating Temperature Technology (HOTTech) and Long-Lived In-Situ Solar System Explorer (LLISSE) projects and the NASA Aeronautics Research Mission Directorate under the Transformational Tools and Technologies (TTT) project. [1] P. Neudeck et al., Proc. 2018 IMAPS Int. High Temperature Electronics Conf. (HiTEC 2018), https://ntrs.nasa.gov/citations/20180003391 . [2] See IC Gen. 12 and IC Gen. 13 Technical Design Primers at https://go.nasa.gov/jfetic