An oxidation-minimizing process using planar MOSFETs has been reported as a technique for achieving high channel mobility by reducing the interface state density (Dit) of the SiC/SiO2 interface. On the other hand, the application of the oxidation-minimizing process to trench MOSFETs has not been reported, and when it is applied, the ripple effect to the industry is extremely large. In order to effectively apply an oxidation-minimizing process to trench MOSFETs, a novel process using LPCVD was proposed to form an extremely thin Si layer on the trench side walls. As a result, the channel mobility was markedly enhanced on a heavily doped p-body, and the normalized on-resistance (RonA) at 473 K was 4.4 % lower than the reference for 400 A-class (6.5 mm□) trench MOSFETs with a BV of over 810 V.