The fast growth of the silicon carbide (SiC) power device market is relying on a sufficient supply of high quality SiC substrate wafers. A reduction of material usage for substrates is highly desirable to reduce device and material costs and secure a steady supply chain. One strategy among others is to use a very thin 4H-SiC layer bonded onto a mechanical carrier. These so-called engineered substrates are regarded as sufficient for epitaxy and device production. In addition to reduced SiC crystal consumption, the device performance can be improved further thanks to lower conduction and switching losses in the device using ultra high conductivity receiver substrates. SOITEC’s SmartCut™ process [1] uses such a 0.6 µm thin monocrystalline SiC layer, which is transferred to a polycrystalline SiC carrier substrate and bonded utilizing a conductive bonding. This study extends a benchmark performed on early samples [2] and looks more into the feasibility for high volume manufacturing using a full cassette to cassette (C2C) epitaxy line. A larger set of current generation 150 mm SOITEC SmartSiC™ wafers will be compared with industry standard bulk wafers from multiple vendors. A first set of similar comparison data will also be presented for 200 mm SOITEC SmartSiC™ wafers and their monocrystalline industry standard competition. For this comparison between standard substrates and engineered wafers we are looking at doping and thickness uniformity as well as the defect performance and predicted device yield. As seen in Fig 1a and Fig 1b, which show two substrates processed in the same epitaxy run, the performance in the doping uniformity is very good and comparable between monolithic and engineered substrates. With respect to the killer defect density, which is an important factor for final device yield, the 150 mm SOITEC SmartSiC™ substrates of the latest generation perform on par with industry standard reference material (see Fig 2). The advanced capabilities of the AIXTRON G10-SiC epitaxy reactors also allow to measure and compare the wafer curvature during the high temperature step, giving insight into residual strain (see Fig 3). No abnormal bow behavior was found on the engineered substrates, and we were able to process them in a fully automated C2C environment with hot loading. This shows the feasibility of engineered SiC substrates for high volume production in epitaxy for silicon carbide power devices. Further details on layer uniformity, defect density and yield – also on 200 mm substrates - will be reported and discussed.