4H-silicon carbide (4H-SiC) metal oxide semiconductor field-effect transistors (MOSFETs) have emerged as viable competitors to their Si insulated-gate bipolar transistor (IGBTs) counterparts, especially in electric vehicle (EV) drivetrains, where these devices typically operate between 600-1200 V [1]. One major challenge that hampers the further uptake of the technology is the increased density of interface traps at the SiO2/SiC interface, which is typically two to three orders of magnitude higher than in Si-based metal-oxide-semiconductor (MOS) systems [2]. Oxide deposition techniques such as atomic layer deposition (ALD) and low-pressure chemical vapour deposition (LPCVD) have already been shown to offer a solution to improve control of the interface and circumvent SiC-specific defects, such as carbon clusters, which are inherent in industry-standard thermal oxidation processes [3]. Post-deposition anneals (PDAs) of ALD SiO2 layers in forming gas (FG) have had a positive impact on both mobility and reliability [3, 4]. In this investigation, we further explore the effect of PDAs on ALD-formed dielectric stacks on 3C-SiC and 4H-SiC MOS-capacitors (MOSCAPs). The dielectric stacks, comprising SiO2, HfO2/SiO2, and Al2O3/SiO2, underwent PDAs across a temperature range from 600°C to 1100°C in either pure N2 or a forming gas (FG) mixture of H2-N2 (5% H2). Figure 1a) shows a schematic of the fabricated 4H-SiC MOSCAP and its corresponding equivalent circuit. Figure 1b) shows a transmission electron microscopy (TEM) image verifies the deposited thickness of stacked dielectrics. C-V and I-V electrical measurements were conducted to analyse interface characteristics such as flat band voltage (VFB), the density of interface traps (Dit), hysteresis (H) and breakdown field (VBD). Dit is extracted from high-low C-V measurements (300 Hz – 1 MHz). Figure 1c) displays representative C-V curves of 4H-SiC MOSCAPs, comparing those that underwent annealing with those that did not. It reveals that the devices without PDA did not achieve complete accumulation. In the full submission, we will report the effect of the PDA on the most promising layers with evidence from secondary-ion mass spectrometry (SIMS), x-ray photoelectron spectroscopy and (XPS) and deep-level transient spectroscopy (DLTS). For an ideal dielectric or dielectric stack, certain characteristics are desired: a high breakdown field a minimal shift in flat band voltage (ΔVFB= φms-VFB, where φms is the difference between metal and semiconductor work function and VFB is the measured flat band voltage) from its ideal value, low Dit, and minimal hysteresis. To evaluate the overall quality of gate dielectrics, a figure of merit (FOM) is proposed, and defined as the ratio of the breakdown field to the product of flatband voltage shift, hysteresis effect, and density of interface states: FOM=V_BD/(∆V_FB*H*D_it). We propose this as a metric to help gauge the effectiveness of gate dielectrics. Figures 2a) and 2c) summarise the individual extracted parameters necessary for calculating the FOM for 3C-SiC and 4H-SiC MOSCAPs. The final calculated FOMs to evaluate the optimum gate dielectric stack and PDA condition for 3C-SiC and 4H-SiC MOSCAPs are shown in Figures 2b) and 2d). In our analysis, we observed that the N2 PDA yields higher figures of merit (FOM) for the 4H-SiC stacks, whereas FG PDA demonstrates higher FOMs, indicating superior interfacial quality, for the 3C-SiC stacks. [1] X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, ‘Review of Silicon Carbide Power Devices and Their Applications’, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8193–8205, Oct. 2017, doi: 10.1109/TIE.2017.2652401. [2]P. Fiorenza, F. Giannazzo, and F. Roccaforte, ‘Characterization of SiO2/4H-SiC interfaces in 4H-SiC MOSFETs: A review’, Energies, vol. 12, no. 12. MDPI AG, 2019. doi: 10.3390/en12122310. [3]A. B. Renz et al., ‘Development of high-quality gate oxide on 4H-SiC using atomic layer deposition’, in Materials Science Forum, Trans Tech Publications Ltd, 2020, pp. 547–553. doi: 10.4028/www.scientific.net/MSF.1004.547. [4]A. B. Renz et al., ‘Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications’, Semicond Sci Technol, vol. 36, no. 5, May 2021, doi: 10.1088/1361-6641/abefa1.