Even though the SiC power MOSFET is an established product by now, there is still plenty of room for improving the transistor’s performance. To exploit the full potential of the superior material properties of SiC, namely the low drift zone resistance due to the high breakdown field strength, other series resistance contributions, such as the channel resistance, must be kept as small as possible. Despite the continuous progress in improving the SiO2/4H-SiC interface and therefore the channel mobility, the channel contribution to the overall RDS,on is still not negligible in most of the SiC power MOSFET products [1]. An innovative approach to minimize the channel contribution is to utilize high-k insulators as gate dielectric material. Due to their higher dielectric constant, the induced inversion charge is increased for the same applied voltage, leading to a reduced channel resistance. Furthermore, most of the high-k dielectrics are deposited by using an ALD process, which offers unique possibilities for in-situ interfacial engineering. However, there are still major challenges, which complicate the integration of these dielectrics into commercially available SiC power MOSFETs. One of them is the relatively low thermal stability of the commonly used high-k materials. During typical SiC power MOSFET production, temperatures up to 1000 °C are needed for ohmic contact formation. Moreover, compatibility with poly-Si gate electrode formation must be ensured. According to literature, these processes often lead to crystallization of the high-k layers, hampering their usage as gate dielectric due to inacceptable leakage currents and reliability issues [2]. In this work, we study the influence of the typical high-temperature processes on the electrical characteristics of poly-Si gated, Al2O3-based MOS capacitors. The schematic cross-section as well as the processing sequence of our MOS capacitors is shown in Fig. 1. We have chosen Al2O3 as the main gate dielectric material due to the relatively high thermal stability and large band-offsets to 4H-SiC. We modified the interfacial properties by using gate dielectric stacks, consisting of 5 nm thin SiO2 and AlN interfacial layers, followed by subsequent Al2O3 deposition. Fig. 2 a) shows the IV breakdown measurements, which were conducted in a cross-shape over the 6” wafers. The wafers #1 and #3 show a high uniformity with an average breakdown field strength around 6,3-6,4 MV/cm. Compared to that, wafer #2 with a 5 nm SiO2 interlayer has a much higher spread with premature breakdowns. Possible root causes for the different behavior of wafer #2 will be discussed at the conference. Fig. 2 b) displays quasi-static CV measurements in up- and down-sweep direction for five different devices per wafer. Especially wafer #1 exhibits a rather small hysteresis with a flat-band voltage close to the ideal one. Moreover, measuring the accumulation capacitance allows the extraction of the relative permittivity εr of the Al2O3 dielectric. The relatively high value of 11,3 could be an indication of possible crystallization of the Al2O3 layer. However, crystallization typically leads to deteriorated electrical performance, which is not observable for wafers #1 and #3. TEM analysis is ongoing and will be shown at the conference to elucidate a fundamental view on the atomistic structure of the investigated gate dielectrics. Due to the excellent uniformity of the IV measurements of wafer #1, constant voltage TDDB measurements at three different temperatures were carried out. An exemplary Weibull plot for a measurement temperature of 175 °C is shown in Fig. 3 a), whereas Fig. 3 b) depicts the intrinsic lifetime extrapolation plotted against the dielectric displacement field D. The D-field is used here instead of the E-field to have a fair comparison between Al2O3 and SiO2, as the D-field accounts for different εr values. Even though the Al2O3 measurement values are highly consistent, the intrinsic lifetime extrapolation yields values below the SiO2 counterpart from commercial SiC production [3], however in the range of 10-100 years. Possible root causes as well as improvement strategy will be part of future research. [1] T. Kimoto, Proceedings of the Japan Academy, Series B 98 (4), 161-189 (2022). [2] R. Lo Nigro et al., Materials 15 (3), 830 (2022). [3] T. Aichinger and M. Schmidt, IEEE International Reliability Physics Symposium (IRPS), 1-6 (2020).