The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Based on material characterisation, we anticipate a benefit of up to 15% or 30% in terms of RDSon for state of the art 1200V SiC MOSFET and JFET. 1200V SiC diodes and 650V MOSFETs have been fabricated by respectively Fraunhofer IISB and ST Microelectronics within the EU funded program Transform. 1200V MPS diodes with voltage drop improvement by 12% and 650V MOSFETs with RDSon improvement by 24% at rated current have been demonstrated. Lowering of the development of SSF is demonstrated after UV illumination, opening the path for robustness to bipolar degradation. Path to reinforce the lifetime of silver sintering die attachment is also foreseen.