To ensure long-term reliable operation of SiC power MOSFETs, it is critical to understand safe operating conditions and the effects of voltage stress on device performance and defectivity, during both operation and testing. The evolution of threshold voltage (VT) and interface trap density (Nit) of SiC MOSFETs during positive high voltage gate stress (HVGS), wherein the oxide field exceeds the threshold for impact ionization, has recently been evaluated [1-2], and it was shown that Nit increases, thereby degrading the MOS interface [2]. In this work, we continue these investigations by studying the evolution of both Nit and field-effect mobility (μFE) during positive as well as negative HVGS on lateral test MOSFETs using ID-VGS and charge pumping (CP) measurements, revealing the practical impact of HVGS on device performance. The devices used for this study are lateral test MOSFETs fabricated on 4° off-axis 4H-SiC epitaxial wafers. The implanted acceptor concentration (NA) in the channel is 2×1017 cm-3 and the MOS interface is formed on the Si face by thermal oxidation followed by NO annealing. The MOSFET channel length and width are 8 μm and 200 μm, respectively. A schematic cross section of the MOSFET is shown in Fig. 1, along with the equations used to calculate µFE and the number of interface traps pumped per cycle (NCP). Each device was stressed at a given gate voltage well beyond the recommended operating condition to induce impact ionization in the oxide for a cumulative stress time of 30 minutes which was interrupted periodically by a CP voltage level sweep with a pulse amplitude of 15 V followed by an I¬D-VGS sweep. Fig. 2 shows the µFE and CP curves after each stress interval for stress voltages of +36 V and -36 V. Positive HVGS causes a significant degradation of both µFE and NCP with time. In addition, VT and the flatband voltage (VFB) quickly shift negatively (within the first minute), then remain nearly constant. This is consistent with past observations and is a consequence of impact generated holes filling pre-existing bulk oxide traps [2]. On the other hand, negative HVGS causes a negligible change in the peak µFE and a small increase in NCP. VT and VFB continuously shift negatively with increasing negative stress time, due to hole trapping in both bulk oxide traps and border traps. The difference in interface trap generation between positive and negative HVGS indicates that the trap generation requires either (i) the presence of hot holes, or (ii) the presence of both electrons and holes, in the oxide near the interface. This can be deduced because positive HVGS causes electrons to be injected from SiC into the SiO2, which can generate holes by impact ionization and/or anode hole injection which will then be accelerated back toward the SiC/SiO2 interface with high energy. But under negative HVGS, holes injected from the interface cannot reach sufficiently high energy to generate electrons, and require a finite distance to accelerate before becoming hot [3]. In Fig. 3 and 4, NCP and µFE are plotted as a function of stress time for different positive and negative stress voltages. Under positive stress, degradation of NCP and µFE increases with both stress voltage and time. Under negative stress, NCP slightly increases but µFE is unaffected. Fig. 5 shows the change in µFE versus the change in NCP during stress with the data for each stress voltage overlaid together. A linear correlation between NCP and µFE is observed for positive HVGS and each stress voltage follows the same universal curve. No correlation is seen for negative HVGS since the mobility does not degrade, perhaps indicating that only donor traps are created during negative HVGS which do not affect the channel mobility. In conclusion, negative HVGS causes significantly less channel degradation in SiC MOSFETs than positive HVGS with respect to interface trap density and channel mobility. Furthermore, CP is shown to be a valuable technique for characterizing SiC MOS degradation. [1] F. Masin et al., J. Appl. Phys., 130, 145702, (2021). [2] S. Stein et al., IEEE IRPS, (2024). [3] D. Arnold et al., Phys. Rev. B, 49, 10278 (1994).