The SiC-gate dielectric interface of SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has to be specifically processed to ensure reliable and highly efficient operation. Namely, the quality of gate dielectric-SiC interface is determined by a presence of (near-) interface traps, leading to reduced channel-carrier mobility and/or threshold voltage drift. This paper presents dynamic capacitor-voltage (C-V) measurements of the metal-dielectric gate stacks, enabling the characterization of the dielectric-semiconductor interface under more device-application relevant conditions than the standard quasi-stationary (QS) C-V measurements.