The performance of silicon carbide MOSFETs is limited by a high density of traps at the oxide semiconductor interface (4H-SiC/SiO2) giving rise to low channel mobility for the MOSFETs. One effective method for quantifying the total interface traps is gated Hall measurements [1,2], which should also allow characterization of any interface degradation effects observed when threshold voltage shift is detected after gate stress [3,4]. In this work, gated Hall measurements are performed to quantify interface traps on the conduction band side of the bandgap. Furthermore, positive gate stress effects have been studied using lateral MOSFET Id-Vg evaluation, and gated Hall measurements. Figure 1 shows a MOS Hall bar top-view. The Hall bar is fabricated on a Si-face 4° off-axis SiC (0001) wafer, on a 2×1017 cm-3 Al-doped p-well. This device is a long channel (Lch=1 mm, Wch=200 um) lateral MOSFET with Hall voltage contacts, fabricated with a thermal oxide passivated with a NO anneal. Figure 2 shows the measured MOS Hall mobility (μ_Hall) and field effect mobility (μ_FE) versus gate voltage at room temperature. The lower value of μ_FE comes due to the high density of interface traps. μ_Hall gives the actual value of the carrier channel mobility, directly measured. The value of the interface trap density is calculated in Fig. 3 from the measured Hall data. First, the total carrier concentration (ntotal) is extracted from a split CV measurement. The free carrier concentration (nfree) is obtained from the gated Hall measurements and then subtracted from ntotal to extract the total trapped charge density (ntrap). As the gate voltage increases, ntrap increases rapidly due to faster occupation of interface traps, while at high gate voltage the trapped charge density increases at a slower rate but doesn’t saturate. These trap levels are in the upper half of the band gap and close to the conduction band edge, the density of which increases exponentially. Hall carrier concentration reveals that about half the channel charge is trapped and not contributing to channel current. Figure 4 shows the Hall and field effect mobilities at different body bias. The values of ntrap are extracted from these measurements as shown in Fig. 5. When the trapped carrier concentrations are plotted as a function of the gate overdrive voltage (Vgs-Vt), all the ntrap curves merge onto each other. This proves that body bias does not change the interface trap densities, only the value of transverse electric field changes, thus changing the mobilities. Next, Hall measurements are used to perform a channel degradation characterization. The gate is stressed at +36 V for different times (0, 10, 30, 100, and 300 sec) and the Hall measurements are performed. Figure 6 shows Hall mobilities as a function of gate overdrive voltage after each stress condition. At low voltage the mobility reduces due to the stress; however, at high gate voltage they overlap. In addition, trapped charge densities are calculated after each gate stress condition. Figure 7 shows that, with increasing stress time, the free carrier density drops, indicating an increase of trapped charge carriers at the interface. Figures 6 and 7 are summarized in Fig. 8 which shows the changes of Nit and mobility (extracted at Vgs-Vt= 15 V) with stress time. Mobility decreases, and the value of Nit increases as the stress time increases. Gated Hall measurements clearly reveal the free and trapped carrier densities and carrier mobility, and is a powerful way to analyze channel degradation under stress, showing the effects on Nit and mobility. [1] M. Noguchi et al., IEEE Trans. Elec. Dev., 68, 12, (2021). [2] S. Das et al., MDPI Materials, 15, 19 (2022). [3] J. Berens et al., IEEE IRPS, pp. 1-5 (2021). [4] A. K. Biswas et al., ICSCRM, accepted (2023).