Although SiC MOSFETs using silicon oxide (SiOx) as gate dielectric are commercially available, with several studies demonstrating their performance and reliability [1-2], the use of high-K (HK) materials for the realization of gate-stacks has demonstrated potential for the fabrication of the next generation of high-performing SiC MOSFETs. This is because HK-based devices offer significant advantages over SiOx-based technologies in terms of improved on-state resistance and minimal threshold voltage hysteresis (VTH,HYS) during switching [3-4]. The reliable and stable operation of SiC MOSFETs is often hindered by the high device-internal electric fields encountered under operating conditions and by the defectivity of the semiconductor-insulator interface leading to charge trapping effects. Reliability/stability characterization relies on accelerated testing occurring under highly accelerated gate bias stress conditions where absolute care must be devoted to avoiding triggering degradation mechanisms not representative of operational conditions. This study addresses the response of an HK-based SiC MOSFET device to high gate voltage stress, comparatively to a SiOx reference, to define the onset of instability mechanisms which are not encountered under operational conditions. The peculiarities of the planar SiC MOSFETs under consideration in this study are summarized in Table I. Additionally, Fig. 1(a)-(b) report the DIT measurements obtained on MOS-capacitors (n-epi) and a schematic representation of the conduction/valence band offset, respectively, representative for the two gate-stack configurations. Comparatively, the HK device exhibits a better semiconductor-insulator interface quality over the SiOx sample, while offering a lower band offset. The DUTs have been exposed to the stress/measurement routine summarized in Fig. 1(c). Here, a positive high voltage gate bias is applied to the DUTs for a total stress time of up to 10 s, while the threshold voltage (VTH) is monitored at regular intervals (10-100 ms) by fast ID-VGS sweeps [5]. The applied gate bias voltages have been calibrated to result in electric field stresses in the dielectrics in the 6 MVcm-1 to 9.5 MVcm-1 range (factors over maximum operating field conditions). Fig. 2(a)-(b) report the VTH monitoring results for the SiOx and HK samples, respectively. For the SiOx sample, electron trapping is observed to be dominating the VTH shift behavior up to a gate stress of 7 MVcm-1. Starting from stresses over 8 MVcm-1, a concurrent process is initiated, leading to a negative VTH variation. Such process is attributed to the trapping of positive charge occurring due to hole generation by impact ionization [6]. Despite the lower band offset exhibited by the HK dielectric, expected to promote hot-electron tunneling and subsequent hole generation, for the HK device the onset of negative VTH shift is observed at larger stress fields (exceeding 9 MVcm-1) and at larger timescales compared to the SiOx device. For stress fields up to 8.5 MVcm-1, the VTH shift behavior for the HK device appears to be still dominated by negative charge trapping, occurring at a fast timescale. Sudden negative VTH shift is observed at 9.25 MVcm-1 (9.5 MVcm-1) for stress times exceeding 2 s (200 ms), highlighting the capability of the employed HK material to inhibit hot-electron injection towards the gate polysilicon. Fig. 3 (a)-(b) show the hysteresis measurements of the sub-threshold characteristics of SiOx and HK devices, respectively, in their pristine state and after undergoing high gate voltage stress at different dielectric fields for 2 s of stress time. The VTH,HYS after the application of each stress is reported in Table II. The VTH,HYS measured for the HK device is significantly smaller than that of the SiOx sample at each stress condition. Additionally, devices stress at 9MVcm-1 have been subjected to a gate voltage stress procedure (TAMB) aimed at the restoration of VTH close to its pristine value. The insert of Fig. 3 and Table. II highlight how for the HK device, the VTH,HYS is fully recovered to its pristine state by the application of a gate bias stress alone.