Name
Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency
Description

Developing an entire process flow for trench structures from the ground up is a time-consuming, expensive, and challenging endeavor, particularly when working with fabrication facilities that lack trench process design kit support. Therefore, our objective is to create a 1.2 kV SiC Trench MOSFET structure that employs the simplest possible process flow and validate its feasibility through TCAD simulation as well as unit process fabrication. This paper introduces the novel concept and fundamental characteristics of the compact 1.2 kV SiC Trench MOSFET with Bottom PWell (BPW), illustrating its optimization using process parameters derived from unit process development. The proposed device is featured by a shallow trench structure with a BPW that can be implemented by ion implantation without necessitating multi- MeV ion implanter.

Speakers
Seung Yup Jang - University at Albany
Date
Monday, September 30, 2024
Time
3:20 PM - 3:40 PM
Location Name
Room 306
Track
Advanced Features in SiC MOSFETs