SiC power MOSFETs are replacing Si devices in the blocking voltage range from 600 to 6500 V with substantial energy saving in various electric systems courtesy to their low on-resistance and fast switching. This trend has been supported by improved channel mobility using a nitridation technique such as NO Post Oxidation Annealing (POA) and now often by using nonplanar structures with higher mobility on non-basal planes [1]. However, the SiO2/SiC interface, POA, has a high density of interface traps (Dit) especially due to carbon-related defects. This is a major cause of reduced channel mobility and threshold voltage instability. Hence a clear industry trend [2] is to replace thermal SiO2 by quality deposited SiO2. Among dielectric deposition techniques, atomic layer deposition (ALD) is widely used due to best-in-class quality of the oxides at low deposition temperature, superior uniformity and conformality, precise control of thickness [3]. The capability to engineer the SiO2/SiC interface by in-situ surface treatment and plasma enhanced ALD (PEALD) of interfacial layers are expected to play a significant role in the manufacturing of high performance SiC MOSFETs. In this study, we utilize cutting-edge ALD technology from Beneq TFS 200 R&D and Transform® high-volume manufacturing cluster tools to fabricate SiO2 dielectric stacks for 4H-SiC MOS capacitors. Furthermore, we investigate in-situ plasma-based surface treatment methods and advanced PEALD techniques with Atomic Layer Annealing (ALA) [4] to tailor the SiC/dielectric interface. The standard fabrication process for 4H-SiC MOS capacitors involves three primary steps: i) plasma precleaning (PP) of the SiC surface to eliminate electrically active defects such as carbon clusters and oxycarbidic phases, ii) deposition of a plasma-based SiO2 interfacial layer (IL) to enhance leakage current, breakdown voltage, and quality of the SiC/SiO2 interface, and iii) deposition of a thick high-quality SiO2 thermal ALD dielectric layer. To investigate the role of the IL, we here used either a 5nm SiO2 by PEALD or a 5nm SiO2 by PEALD with ALA. Fig. 1 (a,b) illustrates measured CV characteristics for devices after N2 anneal, and (c) shows extracted hysteresis, (d) flat band voltage, and (e) trapped charge. The PP/IL/SiO2 samples with PEALD SiO2 IL exhibit a sharp CV profile with a narrow hysteresis of 0.5V and a VFB of 1.63V. Furthermore, devices with the PEALD SiO2 ALA IL (PP/ALA IL/SiO2) demonstrate a substantial reduction in hysteresis to 0.09V, accompanied by a nearly ideal VFB of 0.94V. These enhancements are attributed to the improved quality of the SiO2 IL by PEALD with ALA, which results in significantly lower charge trapping at the SiO2/SiC interface from - 3 × 1011 to 6 × 1010 cm-2 which is near the detection limit. Given potential charge trapping in the bulk of the dielectric layer, we revised the deposition conditions for the ALD SiO2 process itself by increasing the deposition temperature. Fig.2 illustrates the electrical characteristics of MOS capacitors fabricated with improved ALD SiO2 deposition conditions using PP only. These devices exhibit a steep CV curve (Fig.2a) and a hysteresis of 0.02V (Fig.2b), representing a 25-fold reduction compared to PP/IL/SiO2 devices. Additionally, the VFB is measured at 0.96V (Fig.2c). The current density-voltage curve (Fig.2d) shows a low leakage current of 2 × 10-7 A/cm2 @4.8 MV/cm (Fig.2e) and a high breakdown voltage of 11.5 MV/cm (Fig.2f), aligning closely with devices featuring SiO2 dielectric layers prepared by high-temperature oxidation process, particularly in terms of breakdown voltage [5]. Currently, devices with PEALD with ALA IL films and an additional low temperature nitridation step are being analyzed for revisited SiO2 deposition conditions, with targeted Dit values well below 1 × 1011 cm-2eV-1. These findings, along with ToF-ERDA elemental composition analysis, will be presented during the conference. Furthermore, the effect of post-deposition annealing with NO and N2 will also be discussed.