Review for Resonac’s SiC Epiwafer Development H. Kanazawa1) 1) Device Solutions Business Unit, Resonac Corporation, 1505 Shimokagemori, Chichibu-shi, Saitama 369-1893, Japan E-mail: kanazawa.hiroshi.xhjhc@resonac.com In January 2023, Showa Denko and Hitachi Chemical were integrated to form the functional chemical manufacturer Resonac. Semiconductor and electronic materials currently account for more than 30% of Resonac Group's sales among its lineup of chemical products, and are expected to achieve the highest operating income by segment. Resonac’s SiC activities for power devices have been started from 1998 and epitaxial wafer business is one of most focused business area in Resonac. SiC devices exhibit a lower specific on-resistance and higher breakdown voltage. However, due to the market requirement for further reliability robustness and the increase for power density of the power module, several defects and dislocations in the epilayer and substrate make this difficult to achieve. Especially, the trend of increase for current density in the device chips requires the reduction of basal plane dislocation (BPD), which is lead to the expansion of the stacking fault during a forward biased operation in a bipolar device. BPDs inducing the bipolar degradation [1] in the epilayer has been eliminated by improving the growing method with conversion to threading edge dislocations (TED) at the epi/sub interface [2], and the BPD detection technique has been also improved using photoluminescence (PL) and X-ray topography[3]. It is known to be difficult to completely determine the device yield using such detection methods, because four types of BPDs converted near the substrate, namely I. At the substrate/buffer layer interface, II. In the buffer layer, III. At the buffer/drift layer interface, IV. Without conversion, could not be identified. (see Fig. 1) We detected the short BPDs using a mirror electron microscope (MEM) technique [4], and we compared the BPD to TED conversion in epilayers grown with the conventional and improved methods. (see Fig. 2) Through the review of latest technical update for our epi-wafer, especially for our best grade of epi [High Grade Epi: 1st, 2nd and 3rd], the status of our Development of epi-wafer is presented. If you want any acknowledgements for your abstract, they should go here. [1] M. Skowronski and S. Ha, J. Appl. Phys. 99 (2006) 011101. [2] N. Ishibashi, K. Fukada, A. Bandoh, K. Momose, and H. Osawa, Mater. Sci. Forum 897 (2017) 55. [3] T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimot, and H. Tsuchida, J. Appl. Phys. 120, (2016) 115101. [4] M. Hasegawa, K. Ohira, N. Kaneoka, T. Ogata, K. Onuki, K. Kobayashi, T. Osanai, K. Masumoto and J. Senzaki, Mater. Sci. Forum 1004, 369-375 (2020).