Ruggedness of Commercial SiC Power Devices: An Urgent Issue

SiC MOSFETs are replacing Si-based devices in electric vehicle (EV) applications due to their excellent performance. To ensure the widespread adoption of SiC MOSFETs in safety-critical applications, a strong focus on reliability and ruggedness is essential. This tutorial will provide an analysis of the reliability and ruggedness of commercial SiC planar and trench MOSFETs of different vendors.

The oxide failure time is an important parameter that reflects the reliability of gate oxides. The impact of three accelerated TDDB tests, namely Constant Voltage Time-Dependent Dielectric Breakdown (CV-TDDB), Pulse Voltage TDDB (PV-TDDB), and Constant Current TDDB (CC-TDDB), on predicting oxide lifetime will be discussed. CV-TDDB is a stress test based on field-driven breakdown, and is widely used in the industry to estimate the lifetime of gate oxides. However, in practical applications, gate control is often achieved using high-frequency pulse signals. Therefore PV-TDDB, which has a stress pattern closer to typical operation, is expected to provide a more accurate prediction of oxide lifetime. CC-TDDB is a stress test based on charge-driven breakdown as the mechanism for gate oxide failure. It avoids the impact of trapped charges on tunneling current and is a faster test method.

Currently, SiC surface defects are a high risk for early gate oxide breakdown, and account for an average 2%-3% device failures of EV inverters in the field. The failure rates are very different for different vendors, especially when planar and trench device architectures are taken into consideration.  In this case, screening technology applied by manufacturers cannot fully remove early failures. Aggressive screening before the device enters the market is still needed to reduce failure rates to 2-3 ppm. The investigation and optimization of wafer-level and package-level screening technology will be discussed in this tutorial.

In addition, degradation due to the body diode’s forward current stress has been evaluated for commercial SiC planar and trench power MOSFETs. We found body diode degradation in trench devices is mainly influenced by the deep P+ implantation and the reactive-ion-etching of trenches that can generate basal plane dislocations. Therefore, embedding a Schottky diode within the trench MOSFET chip may be beneficial. Furthermore, commercial SiC planar MOSFETs show notably reduced short-circuit withstand times (SCWT), ranging from 1.7 µs to 3.6 µs, compared with Si IGBTs that have a SCWT of ≥ 10 µs. SiC asymmetric trench and double trench MOSFETs exhibit longer SCWT than SiC planar MOSFETs. The longer SCWT of trench MOSFETs may be due to the deep p-type implant regions that shield the MOS channel from high drain voltage. The efficacy of deep P-well through channel implantation has been shown to enhance SCWT in planar MOSFETs.

Another form of failure in SiC MOSFETs is induced by high drain voltage, and is detected by accelerated High Temperature Reverse Bias (HTRB) testing.  It is related to the design of the edge termination as well as the bulk defects in SiC.  Preliminary results will be briefly introduced.

Finally, rapid screening of incoming power modules in the inverter factory is of immense importance.  Prediction and screening of large numbers of parts with respect to latent failures in gate oxide, body diode degradation, reduced SCWT, and drain-source blocking voltage is of critical importance and must be addressed by EV manufacturers.