SiC Power MOSFET Design from the Ground Up

Power electronic systems are a foundational building block of our modern world. These systems contain large discrete transistors and diodes that can block high voltages and control the flow of high currents. Until recently, the transistors used in such systems were primarily silicon MOSFETs and IGBTs. However, since 2011, SiC MOSFETs have steadily displaced their Si counterparts, and have rapidly developed into a multibillion-dollar industry. This is due in large part to the ~ 8x higher critical field of SiC vs. silicon, which enables unipolar devices such as MOSFETs and Schottky diodes to have dramatically lower on-state resistance.

This tutorial will provide attendees, who have a basic familiarity with a logic-style MOSFETs, with an understanding of how a SiC power MOSFET is designed and fabricated. The talk will start with a discussion of how diodes and transistors are designed to withstand high voltages in the off-state. We will discuss the relationship between blocking voltage and on-state resistance, and show how the latter can be minimized. While other device geometries may be briefly discussed, the tutorial will focus on the most common implementation of a power transistor, the vertical DMOSFET.

After introducing the basic device structure, a typical process flow used to fabricate SiC DMOSFETs will be presented, focusing on aspects that are unique to SiC. This will be followed by a discussion of design optimization, particularly focused on applications where the channel resistance is a significant factor. Topics will include retrograde body doping profiles, shielding of the gate oxide from high fields, design and doping of the “JFET” region, and current spreading layers. Different top-view layout strategies will be discussed, including linear and cellular designs, segmented body contacts, and edge termination schemes.